module ctr_seq (CurState, NextState, clk, rst);

    output  [2:0]   CurState;
    input   [2:0]   NextState;
    input           clk;
    input           rst;

    dff bit[2:0]    (.q(CurState),.d(NextState),.clk(clk),.rst(rst));

endmodule
